ORCONF 2013 Next Month – Free and Open Source Silicon Chip Design for All

Jeremy Bennett
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The annual OpenCores conference is now in its third year and comes to the UK for the first time. We’ll be meeting on 5-6 October at the Cambridge University Computer Laboratory. This is the ultimate informal conference, where all of those interested in open source silicon chip design can get together to talk, design, eat and drink.

The program is a mixture of talks and workshops. Julius Baxter will be bringing you the latest on his mor1kx, a new implementation of the OpenRISC 1000 architecture. There are three variants of the implementation: one with 2-stage pipeline with delay slot (espresso), one with 2-stage pipeline without delay slot (pronto espresso), and another with a 6-stage pipeline (cappuccino). For comparison the original OR1200 had a 4/5-stage pipeline. Julius will talk about the implementation and its performance, and all being well, he’ll give a demo.

Looking forward to future developments of OpenRISC, Stefan Wallentowitz of TU Munich will be talking about his many-core OpenRISC project, OpTiMSoC. It has been a common request to use OpenRISC in multi-core applications, and Stefan’s work provides the basis for this. David Greaves of Cambridge University Computer Laboratory will also be talking about his multi-core TLM SystemC OpenRISC, which features power annotation.

Martin Schulze will be talking about his research into defining a Domain Specific Language for the configuration of SoCs based on the OpenRISC Platform — work he carried out for his bachelor thesis in Germany.

For a couple of years there have been ideas for a successor to the OpenRISC 1000 architecture, the OpenRISC 2000. While inspired by OR1K, it is neither forwards nor backwards compatible. We’ll have a discussion session where we try to bring the OR2K to a position where a keen enthusiast could start implementation.

Most people use the OpenRISC processor as part of a complete System-on-Chip. The granddaddy of all these is ORPSoC, the OpenRISC Reference Platform SoC, now in its 3rd version. There will be a hands-on session introducing ORPSoCv3 and its design.

We’re also planning a couple of workshops. The first will show how to bring up ORPSoC on a DE0-nano. We’ll have a number of DE0-nano boards available, and over a 90-minute session you should gain the skills necessary to get it working.  If you are new to SoC design, this is the session for you! The second workshop is something of a tradition — well we did it last year anyway — a bug scrub at the end of the conference. This is a great way for the community to get together to clean up all those irritating little problems that have been hanging around.

Finally, it’s not all engineering. Cambridge is famous for its eating and drinking, and on Saturday night we’ll gather together for the conference dinner in one of Cambridge’s many pubs.

You can still sign up — note the meeting is free to attend — at EventBrite. We look forward to seeing you there!

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