Hardware logic model which is based only on logic high and logic low (binary 0 and binary 1) values.

See also 4-state

Hardware logic model which considers unknown (X) and unproven (Z) values as well as logic high and logic low (binary 0 and binary 1).

See also 2-state

The low-level interface between an application program and the operating system, thus ensuring binary compatibility between programs.

C++ notoriously suffers from lack of agreed standards in this area.

In TLM 2.0 a modeling style where timing information is provided at the level of transactions representing the phases of data transfer in a specific bus protocol (for example the address and data phases of an AHB read or write).

See also loosely timed, phase

In TLM 2.0 non-blocking transport, the transport function which returns the response transaction from target to initiator.

See also transport function, forward transport path

A description of the relationship between byte and word addressing on a computer architecture. In a big endian architecture, the least significant byte in a data word resides at the highest byte address (of the bytes in the word) in memory.

The alternative is little endian addressing.

See also little endian

In object oriented programming a class from which other classes (the derived classes) are derived, inheriting variables and functions. Specifically a term favored by C++, also referred to as a parent class or super-class.

See also derived class

Within the context of TLM, a transaction which blocks the flow of control in the initiator until the target has completed the transaction request and responded.

See also non-blocking

A TLM 2.0 wrapper, providing for simple TLM communication based on C++ callbacks.

In object oriented programming a class which has inheriting variables and functions from another class (known as the base class). Specifically a term favored by C++, also referred to as a child class or subclass.

See also base class

In hardware and software design communication between memory and a peripheral without the constant intervention of the processor.

In TLM 2.0 communication between two threads (typically representing a processor and a memory block) by direct writing through a pointer to the memory rather than by a transactional exchange.

See also transport function, backward transport path

In TLM 2.0 non-blocking transport the transport function, which passes the opening transaction from initiator to target.

See also transport function, backward transport path

Within TLM 2.0, a class suitable for use as payload for transactions. Recommended to maximize the interoperability of TLMs.

See also payload, generic payload extension

Within TLM 2.0, a mechanism for extending the generic payload, thus allowing initiators and targets to specify additional information.

In its simplest form, extensions are ignorable. Initiators and targets will work correctly if the extension is not present.

Extensions may also be mandatory. This is for use where the additional information provided is necessary for initiators and targets to work correctly.

See also payload, generic payload extension

A language (Verilog and VHDL are the best known), which describes hardware. Can be used to describe both an actual chip and its test bench.

The initiator of a transactional exchange to a target. In TLM 2.0 an initiator module must implement an initiator socket of the appropriate type (blocking or non-blocking).

See also target

A software model of a CPU core instruction set. Typically completely models the instruction semantics, but not the full microarchitecture of a particular CPU implementation. Timing information may be just an instruction count, or may (as with the Or1ksim) offer some estimate of timing delays due to memory accesses, caching and virtual memory access.

JTAG is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards and chips using boundary scan.

This standard allows external reading of state within the board or chip. It is thus a natural mechanism for debuggers to connect to embedded systems.

See Open SystemC Initiative.

A description of the relationship between byte and word addressing on a computer architecture. In a little endian architecture, the least significant byte in a data word resides at the lowest byte address (of the bytes in the word) in memory.

The alternative is big endian addressing.

See also big endian

In TLM 2.0 a modeling style, where timing information is provided at the level of transactions representing a complete data transfer across a hardware bus.

See also approximately timed

A hardware component which maps virtual address references to physical memory addresses via a page lookup table. An exception handler may be required to bring non-existent memory pages into physical memory from backing storage when accessed.

On a Harvard architecture (i.e. with separate logical instruction and data address spaces), two MMUs are typically needed.

An object in a program which provides a lock, used to negotiate mutual exclusion between multiple threads.

SystemC provides a sc_mutex class to implement mutual exclusion between SystemC threads.

Within the context of TLM, a transaction which allows the flow of control in the initiator to continue immediately the transaction is sent. The response will be provided later by a transport call from the target back to the initiator..

See also blocking

A term describing a TLM 2.0 convenience socket which does not perform an automatic conversion between blocking and non-blocking transport. Potentially more efficient than the other types of convenience socket.

See also payload

The data passed between threads by a transaction.

See also generic payload

See generic payload extension.

In TLM 2.0 approximately timed modeling, a transaction exchange representing a single phase of the specific bus protocol being modeled (for example the address phase of an AHB read or write).

See also approximately timed

An IEEE standard for application programming interfaces and utilities for Unix/Linux operating systems.

A hardware component which provides a large number of interrupt ports, which are mapped onto one or two interrupt ports on an actual processor. The PIC will provide a lookup table of interrupt service functions for its interrupts, which the interrupt service function on the processor can use to identify the correct handler to use.

In TLM 2.0 with temporal decoupling, the maximum time a thread may run ahead of the main system clock. This may be regulated by a quantum keeper.

See also temporal decoupling, quantum keeper

In TLM 2.0 with temporal decoupling, an object which enforces the rule that threads may not run more than the quantum ahead of the main system clock

See also temporal decoupling, quantum

In object oriented programming, a class which can have at most one instance. Typically implemented by making the constructor private and providing an access function which instantiates the class on its first call and on all other calls returns a pointer to that instance.

Within the context of TLM 2.0, a SystemC port and export combined with the associated interfaces for blocking and non-blocking transport, direct memory access and debug.

See also SystemC

A set of libraries and macros, which extend the C++ programming language to facilitate modeling of hardware.

Standardized by the Open SystemC Initiative, who provide an open source reference implementation.

See also Open SystemC Initiative

A silicon chip which includes one or more processor cores.

A TLM 2.0 convenience socket, which incorporates a numerical tag to identify the socket in use. This allows a single callback function to handle multiple sockets, with the tag identifying the socket which caused the callback to be invoked.

See also socket

The responder to a transactional exchange initiated by an initiator. In TLM 2.0 a target module must implement a target socket of the appropriate type (blocking or non-blocking).

See also initiator

In TLM 2.0 the concept of allowing individual threads to run ahead of the main simulation time stamp. The maximum permitted time of run ahead is known as the quantum and may be regulated by a quantum keeper.

See also quantum, quantum keeper

The interface to a JTAG interface defined by IEEE 1149.1.

In software, a logical parallel flow of control. In the context of SystemC, the main function of such a thread can be specified with the SC_THREAD macro. In SystemC a SC_THREAD is distinguished from a SC_METHOD because it can suspend execution with wait calls.

See also SystemC

An abbreviation for (depending on context) Transaction Level Model or Transaction Level Modeling.

See also Transaction Level Model, Transaction Level Modeling

The OSCI standard interface for writing Transaction Level Models in SystemC.

See also Transaction Level Model, SystemC

In TLM modeling the exchange of data between two threads.

The C++ function which transfers data from an initiator to a target, and (for a non-blocking interface), the response back from the target to the initiator. Within the context of TLM 2.0 blocking and non-blocking transport interfaces are defined.

See also SystemC

An exchange of data (the payload) between two parallel processes. In TLM 2.0 this transaction occurs through SystemC ports implementing the TLM 2.0 interfaces, which are known as sockets.

A full description is provided in Section 2.2.

See also payload, socket

A software model in which the components of the model communicate by transferring information to and from each other (transactions).

A full description is provided in Section 2.2.

The process of writing software models using Transaction Level Model

See also Transaction Level Model