	Services and Modeling for Embedded Software Development

Building a Loosely Timed SoC Model with OSCI TLM 2.0

A Case Study Using an Open Source ISS and Linux 2.6 Kernel

Jeremy Bennett

Embecosm

Application Note 1. Issue 2

May 2010

Copyright © 2008, 2010 Embecosm Limited

Creative Commons License

The document entitled " Building a Loosely Timed SoC Model with OSCI TLM 2.0 " by Jeremy Bennett of Embecosm is licensed under a Creative Commons Attribution 2.0 UK: England & Wales License. See the Legal Notice for details.

Table of Contents

1. Introduction

1.1. New in Issue 2
1.2. Target Audience
1.3. About the Embecosm TLM 2.0 Application Notes
1.4. Acknowledgment

2. Background to SystemC and the TLM 2.0 Standard

2.1. What is SystemC

2.2. What is a TLM

2.2.1. Hardware and Software Views of Parallelism
2.2.2. Modeling Hardware Parallelism in Software

2.3. Overview of OSCI TLM 2.0

2.3.1. Transaction Payload
2.3.2. Initiators and Targets
2.3.3. Blocking, Non-Blocking, Debug and Direct Memory Interfaces
2.3.4. Loosely Timed, Approximately Timed and Untimed TLM
2.3.5. TLM 2.0 Convenience Sockets

3. Case Study: A Loosely Timed SoC Using TLM 2.0

3.1. The Example Designs

3.1.1. Or1ksim ISS TLM 2.0 Wrapper with Logger
3.1.2. Simple SoC Design
3.1.3. SoC with Interrupt Support
3.1.4. SoC with Debugger Support

3.2. Example Code

3.2.1. Source Code for Example Models and Programs
3.2.2. Code Documentation
3.2.3. SystemC Model Coding Conventions
3.2.4. Derived classes
3.2.5. Configuration

4. Wrapping the ISS

4.1. Modifying the Or1ksim ISS for TLM 2.0

4.1.1. Converting Or1ksim to a Library
4.1.2. Additional Functionality for Or1ksim

4.2. Or1ksim Wrapper Module Class Definition

4.2.1. Included Headers
4.2.2. Module Declaration
4.2.3. Constructor and Destructor
4.2.4. Public Interface
4.2.5. Threads
4.2.6. Upcalls

4.3. Or1ksim Wrapper Module Class Implementation

4.3.1. Headers and Macros
4.3.2. Constructor
4.3.3. Thread
4.3.4. Upcalls
4.3.5. Blocking Transport

5. Testing the Or1ksim ISS TLM 2.0 Wrapper

5.1. Overall Design of the Test Program

5.1.1. Class Structure
5.1.2. Behavioral Diagrams

5.2. Definition of the TLM 2.0 Logger Module

5.2.1. Include Files
5.2.2. Module Declaration and Constructor
5.2.3. Public Interface
5.2.4. Blocking Transport

5.3. Implementation of the TLM 2.0 Logger Module

5.3.1. Included Headers
5.3.2. Constructor
5.3.3. Blocking Transport Callback

5.4. The Model Main Program

5.4.1. Included Headers
5.4.2. Argument Processing
5.4.3. Module Instantiation
5.4.4. Connecting the Modules
5.4.5. Model Execution

5.5. Test Program to Run on the Or1ksim

5.5.1. The Utility Functions
5.5.2. Memory Mapped Data Structure
5.5.3. Checking Write Access
5.5.4. Checking Read Access
5.5.5. Program Compilation

5.6. Running the Test

5.6.1. Compiling the SystemC Model
5.6.2. Configuring the OpenRISC 1000 Or1ksim ISS
5.6.3. Running the Compiled Model

6. Modeling Peripherals

6.1. Details of the 16450 UART

6.2. UART Module Design

6.2.1. UART Model Interfaces
6.2.2. UART Model Registers
6.2.3. UART Model Interrupts

6.3. Extending the Or1ksimSC Wrapper Module

6.3.1. Adding an Endianness Test Function to the Or1ksim Library
6.3.2. Extended Or1ksim Wrapper Module Class Definition
6.3.3. Extended Or1ksim Wrapper Module Class Implementation

6.4. UART: Module Class Definition

6.4.1. Headers and Constant Definitions
6.4.2. Class Declaration and Constructor
6.4.3. Public Interface
6.4.4. SystemC Processes
6.4.5. Blocking Transport Callback
6.4.6. Utility Functions
6.4.7. UART State
6.4.8. Notifying the Bus Thread of Transaction Activity

6.5. UART Module Class Implementation

6.5.1. UART Constructor
6.5.2. UART Processes
6.5.3. UART Blocking Transport Callback
6.5.4. UART Read Behavior
6.5.5. UART Write Behavior
6.5.6. UART Utility Functions

7. Adding a Terminal as a Test Bench

7.1. Overall Design of the Simple SoC Model

7.1.1. Class Structure
7.1.2. Behavioral Diagrams

7.2. SystemC Terminal Module Design

7.3. Terminal Module Class Definition

7.3.1. Mapping Signals to Class Instances
7.3.2. The SystemC Class
7.3.3. Setting up the xterm
7.3.4. Signal and event handling

7.4. Terminal Module Class Implementation

7.4.1. SystemC Processes
7.4.2. Signal and event handling

7.5. The Complete SoC

7.5.1. The Model Main Program
7.5.2. Test Program to Run on the Or1ksim ISS
7.5.3. Compiling and Running the Model
7.5.4. Model Timing

8. Adding Synchronous Timing to the Model

8.1. Summary of Changes Required for Synchronous Timing

8.2. Overall Design of the Synchronized SoC Model

8.2.1. Class Structure
8.2.2. Behavioral Diagrams

8.3. Extending the Or1ksimExtSC Wrapper Module

8.3.1. Adding Clock Rate and Timing Functions to the Or1ksim Library
8.3.2. Or1ksimSyncSC Module Class Definition
8.3.3. Or1ksimSyncSC Module Class Implementation

8.4. Extending the UartSC Module Class

8.4.1. UartSyncSC Module Class Definition
8.4.2. UartSyncSC Module Class Implementation

8.5. Extending the TermSC Module Class

8.5.1. TermSyncSC Module Class Definition
8.5.2. TermSyncSC Module Class Implementation

8.6. Main Program for the Synchronous Model

8.7. Compiling and Running the Synchronous Model

9. Adding Temporal Decoupling to the Model

9.1. What is Temporal Decoupling

9.1.1. Timing Concepts
9.1.2. The Global Quantum Class, tlm_global_quantum
9.1.3. TLM 2.0 Quantum Keepers
9.1.4. Other Styles of Temporal Decoupling

9.2. Guidelines for Using TLM 2.0 Temporal Decoupling

9.3. Overall Design of the Temporally Decoupled SoC Model

9.3.1. Class Structure
9.3.2. Behavioral Diagrams

9.4. Temporal Decoupling the Or1ksim Wrapper Class

9.4.1. Adding a Function to the Or1ksim Library to Support Temporal Decoupling
9.4.2. Or1ksimDecoupSC Module Class Definition
9.4.3. Or1ksimDecoupSC Module Class Implementation

9.5. Modifying the UART to Support Temporal Decoupling

9.5.1. uartDecoupSC Module Class Definition
9.5.2. uartDecoupSC Module Class Implementation

9.6. Main Program for Temporal Decoupling

9.7. Compiling and Running the Decoupled Model

10. Modeling Interrupts and Running Linux on the Example SoC

10.1. Overall Design of the SoC Model with Interrupts

10.1.1. Class Structure
10.1.2. Behavioral Diagrams

10.2. Extending the Or1ksimDecoupSC Module Class

10.2.1. Adding Interrupt Generation Functions to the Or1ksim Library
10.2.2. Or1ksimIntrSC Module Class Definition
10.2.3. Or1ksimIntrSC Module Class Implementation

10.3. Extending the UartDecoupSC Module Class

10.3.1. UartIntrSC Module Class Definition
10.3.2. UartIntrSC Module Class Implementation

10.4. Main Program for the Interrupt Driven Model

10.5. Running the Interrupt Driven Model

10.5.1. Simple Test for the Interrupt Driven SoC Model
10.5.2. Running Linux

11. Adding a JTAG Interface to the Model

11.1. Overall Design of the SoC Model with JTAG Interface

11.1.1. Class Structure
11.1.2. Behavioral Diagrams

11.2. A TLM 2.0 Interface for JTAG Using a Payload Extension

11.2.1. JtagExtensionSC Extension Class Definition
11.2.2. JtagExtensionSC Extension Class Implementation

11.3. Extending the Or1ksimIntrSC Module Class

11.3.1. Adding JTAG Interface Functions to the Or1ksim library
11.3.2. Or1ksimJtagSC Module Class Definition
11.3.3. Or1ksimJtagSC Module Class Implementation

11.4. A JTAG Traffic Generating Class

11.4.1. JtagLoggerSC Module Class Definition
11.4.2. JtagLoggerSC Module Class Implementation

11.5. Main Program for the Model with JTAG Debug Interface

11.6. Running the Model with JTAG Debug Interface

11.6.1. Simple Test for the Model with JTAG Debug Interface

A. Downloading the Example Models

A.1. Configuring and Building
A.2. Building the Linux Kernel

B. Running with Mac OS

Next

Chapter 1. Introduction

Copyright © 2008, 2010 Embecosm Limited