3.1. The OpenRISC 1000 JTAG Interface

There are two variants of the JTAG interface for use with the OpenRISC 1000.

The original JTAG interface was created as part of the OpenRISC SoC project, ORPSoC [10]. It provides three scan chains: one to access to all the SPRs, one to access external memory and one providing control of the CPU. The control scan chain reset, stall or trace the processor.
A new JTAG interface was provided by Igor Mohor in 2004 [11]. It provides the same access to SPRs and external memory, but offers a simpler control interface offering only the ability to stall or reset the processor.

At present the OpenRISC Architectural Simulator, Or1ksim, (see Section 3.4) supports the first of these interfaces.

Three scan chains are provided by both interfaces

RISC_DEBUG (scan chain 1), providing read/write access to the SPRs.
REGISTER (scan chain 4), providing control of the CPU. In the ORPSoC interface, this provides multiple registers which are read and written to control the CPU. Of these register 0, MODER, which controls hardware trace, and register 4, RISC_OP, which controls reset and stall are the most important. Trace is enabled by setting, and disabled by clearing bit 1 in MODER. Reset and processor stall are triggered and cleared by setting and clearing respectively bit 1 and bit 0 in RISC_OP. The stall state may be determined by reading the stall bit in RISC_OP.
In the Mohor interface, there is a single control register which behaves identically to RISC_OP in the original debug interface.
WISHBONE (scan chain 5), providing read/write access to main memory.

Since the General Purpose Registers (GPRs) are mapped to SPR group 0, this mechanism also allows GPRs to be read and written.