4.1.1. The OpenRISC 1000 Architecture

The OpenRISC 1000 architecture defines a family of free, open source RISC processor cores. It is a 32 or 64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility.

The OpenRISC 1000 is fully documented in its Architecture Manual [6].

From a debugging perspective, there are three data areas that are manipulated by the instruction set.

Main memory. A uniform address space with 32 or 64-bit addressing. Provision for separate or unified instruction and data and instruction caches. Provision for separate or unified, 1 or 2-level data and instruction MMUs.
General Purpose Registers (GPRs). Up to 32 registers, 32 or 64-bit in length.
Special Purpose Registers (SPRs). Up to 32 groups each with up to 2048 registers, up to 32 or 64-bit in length. These registers provide all the administrative functionality of the processor: program counter, processor status, saved exception registers, debug interface, MMU and cache interfaces, etc.

The Special Purpose Registers (SPRs) represent a challenge for GDB, since they represent neither addressable memory, nor have the characteristics of a register set (generally modest in number).

A number of SPRs are of particular significance to the GDB implementation.

Configuration registers. The Unit Present register (SPR 1, UPR), CPU Configuration register (SPR 2, CPUCFGR) and Debug Configuration register (SPR 7, DCFGR) identify the features available in the particular OpenRISC 1000 implementation. This includes the instruction set in use, number of general purpose registers and configuration of the hardware debug interface.
Program counters. The Previous Program Counter (SPR 0x12, PPC) is the address of the instruction just executed. The Next Program Counter (SPR 0x10, NPC) is the address of the next instruction to be executed. The NPC is the value reported by GDBs $pc variable.
Supervision Register. The supervision register (SPR 0x11, SR) represents the current status of the processor. It is the value reported by GDBs status register variable, $ps.