The program counter (i.e. the address of the next instruction to be executed) is held in Special Purpose Register 16 (next program counter). Within Or1ksim this is cached in cpu_state.pc.

When changing the next program counter in Or1ksim it is necessary to change associated data which controls the delay slot pipeline. If there is a delayed transfer, the flag cpu_state.delay_insn is set. The address of the next instruction to be executed (which is affected by the delay slot) is held in the global variable, pc_next.

The utility function set_npc () takes an address as argument. If that address is different to the current value of NPC, then the NPC (in cpu_state.pc) is updated to the new address, the delay slot pipeline is cleared (cpu_state.delay_insn is set to zero) and the following instruction (pcnext) is set to cpu_state.pc+4.