|
Verilator is the fastest free Verilog HDL cycle
accurate simulator. It compiles synthesizable
Verilog (not test-bench code!), plus some PSL,
SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large
projects where fast simulation performance is of
primary concern, and is especially well suited
to generate executable models of CPUs for
embedded software design teams.
Embecosm provides support services for companies
using Verilator in a commercial environment. We
can also develop new features, such as
additional language support or new optimization
approaches. In this way commercial adoption
furthers the development of this open source
tool.
|