Using JTAG with SystemC

Implementation of a Cycle Accurate Interface

Embecosm Application Note EAN 5
Issue 1, January 2009

This application note is aimed at engineers needing to interface SystemC to cycle accurate models of devices implementing the IEEE 1149.1 JTAG interface.

Typical uses are:

• Development of SystemC testbenches for cycle accurate models, or to drive hardware emulation.

• Interfacing tools such as debuggers to cycle accurate models written in SystemC.

Cycle accurate models of devices in SystemC may be written by hand. More commonly they are generated automatically by tools such as Verilator, ARC VTOC and Carbon Design Systems ModelStudio. They may also be implemented using SystemC interfaces to traditional event driven simulation.

Directly interfacing to the JTAG cycle accurate ports of a SystemC model is a complex task, requiring careful modeling of the JTAG Test Access Port (TAP) state machine.

This application note specifies a more abstract interface, allowing the user to simply read and write hardware registers through JTAG. The interface takes responsibility for ensuring the correct sequence of signals is sent through the TAP to achieve the desired action.

The interface is implemented as SystemC module with a FIFO on which the user queues requests, and signal ports to which the low level JTAG pins are connected. The module handles and generates the appropriate signals for the JTAG TAP pins (TCK, TDI, TDO, TMS and TRST).

The application note and its associated reference implementation provide a practical tool for engineers involved in the detailed design, verification and modeling of complex FPGAs and ASICs.

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This application note is licensed under a Creative Commons Attribution 2.0 License.

A reference implementation of the cycle accurate SystemC JTAG interface is provided as Embecosm Software Package ESP 4, Cycle Accurate SystemC JTAG Interface: Reference Implementation.