High Performance SoC Modeling with Verilator

A Tutorial for Cycle Accurate SystemC Model Creation and Optimization

Embecosm Application Note EAN 6
Issue 1, February 2009

This application note is a tutorial in building high performance SystemC cycle accurate models from Verilog RTL.

Typical uses are:

• Detailed performance analysis of systems, based on the actual hardware implementation running with its embedded software.

• Implementation of low level firmware, such as board support packages, codecs and specialist device drivers, which rely on exact behavior of SoC peripherals.

• Software optimization of components such as device drivers and codecs, where optimal performance depends on precise integration with the hardware architecture.

This tutorial uses the open source tool, Verilator. However the same techniques are of value with commercial tools such as ARC VTOC and Carbon Design Systems' ModelStudio.

The tutorial demonstrates the techniques using the OpenRISC Reference Platform System-on-Chip (ORPSoC), a 32-bit SoC. An initial event-driven simulation at 1.4kHz is replaced by a cycle accurate SystemC model, running at 130kHz.

Embecosm are also able to present the content of this tutorial as a two day seminar. Please contact us for more details.

Browse the application note online as

• single file HTML

• multi-file HTML

Download the application note as

• PDF

• Single file HTML (zip, tar.bz2)

• Multi-file HTML (zip, tar.bz2)

• Source DocBook XML (zip, tar.bz2).

This application note is licensed under a Creative Commons Attribution 2.0 License.

The example used in this application note is provided as Embecosm Software Package ESP 5, Cycle Accurate SystemC Model of a 32-bit SoC.