Modeling

Productive early firmware development requires models of not just the processor, but the peripheral components and the environment in which the SoC will be used. An instruction set simulator of just the CPU is not sufficient.

For application development, fast high level models are required, offering good performance, but at the expense of detailed modeling accuracy. For device driver optimization and performance analysis fully cycle accurate models are essential.

Developing these models reliably, and in short time frames is a challenge. Embecosm has the skills and experience to supply them.

• Hand coded high level functional models of custom peripherals;
• Conversion of existing models to the latest OSCI SystemC TLM 2.0 standard;
• Cycle accurate models generated from hardware descriptions using tools such as Verilator or ARC VTOC; and
• Graphical models of the external environment, allowing the functionality of the developed software to be visualized realistically.
• Hands-on training seminars in modeling techniques specifically for firmware development.

Embecosm's application note on modeling and model reuse was the first publication to explain how to use the new OSCI SystemC TLM 2.0 standard for complete SoCs (more information).

Embecosm has defined a new standard interface for cycle accurate SystemC modeling using JTAG, for simpler interfacing to low level SystemC models. Our reference implementation means this technology can be adopted with minimal work by the user (more information).

The Embecosm application notes on cycle accurate modeling with Verilator and interfacing the GNU Debugger to cycle accurate models are the standard references for this technology. They show how a complete System-on-Chip can be converted automatically to a cycle accurate SystemC model, and then interfaced to the GNU Debugger for firmware development.