Unified SoC Firmware Debugging and Development

There are three key features of Embecosm's unique tools and technology:

1. The same debugging interface is presented throughout the design life cycle, from initial model to final silicon.

2. The engineer has visibility not just of the processor being debugged, but all the peripherals of the System-on-Chip.

3. The implementation uses existing standard protocols and interfaces.

The Embecosm approach ensures the firmware development team have a consistent and reliable debugging interface from initial system design through to functional silicon. Firmware development can start earlier and is far more productive. By starting early, any problems uncovered in the hardware can be fixed before tapeout, helping to avoid costly respins of silicon.

Our technology pages give more information on the underlying engineering.

Reference Implementation

Embecosm provides a reference implementation, supporting the GNU Debugger interfacing to the OpenRISC 1000 Reference Platform SoC (ORPSoC) via an IEEE 1149.1 five wire JTAG port.

The reference implementation provides adapters for the following target types via the abstract JTAG interface.

• SystemC TLM 2.0 loosely timed transactional inteface to a high speed SystemC model of the SoC.

• SystemC 2.2 cycle accurate interface to a SystemC model generated by Verilator from the Verilog of the SoC.

• IEEE 1364-2005 Verilog Procedural Interface (VPI) to event driven simulation of the SoC

• FTDI 2232C USB to JTAG interface to drive an FPGA implementation of the SoC.

The reference implementation allows users to evaluate the power of this technology, and forms a starting point for porting to other target architectures

Availability and Support

SystemC TLM 2.0 loosely timed and SystemC 2.2 cycle accurate interfaces are currently released. VPI and FTDI interfaces will be available during Q2 2010.

All services come with an initial 3 month support package, which can be extended as desired.

Embecosm Services

Embecosm provides the following services for customers wishing to adopt this technology.

• Migrate Existing GDB. An existing GDB implementation is migrated to the Embecosm Unified Debug Interface using JTAG.

  A GDB Remote Serial Protocol server is provided for the target architecture. It will drive all of the available JTAG targets (model and fixed silicon).

  This service can be supplied as a fixed price package.

• Implement GDB. For designs where no GDB implementation exists.

  A new GDB client implementation is provided and a GDB Remote Serial Protocol server is provided for the target architecture using the Embecosm Unified Debug Interface. It will drive all of the available JTAG targets (model and fixed silicon).

  Option. Embecosm can manage introduction of the new GDB port into the mainstream FSF GDB distribution and provide ongoing maintenance of the code to ensure consistency within the mainstream distribution.

  This service can be supplied as a fixed price package.

• Support a New Hardware Interface. For users based on JTAG, but who require a different physical or modeled interface (for example an alternative to the FTDI 2232C USB).

  A new JTAG adapter is written and integrated with the GDB Remote Serial Protocol server for the target architecture. It will work seamlessly alongside all the existing JTAG targets (model and fixed silicon).

• Support a New Debug Interface. For users who are not using JTAG. The Embecosm Unified Debug Interface is completely generic and can drive a wide range of debug interfaces.

  A new abstract representation of the interface is defined and adapters written for the various required model and silicon targets. The interface is then integrated with the Remote Serial Protocol Server to provide debugging support for all targets.

• Support a Different Debugger. For users who are not using GDB. The Embecosm Unified Debug Interface is completely generic and can work with a wide range of different debuggers.

  A new abstract representation of a remote server for the debugger is written. A concrete subclass for the specific target architecture is implemented and integrated with the hardware debug interface abstraction (for example JTAG) and its adapters, allowing the debugger to drive all model and physical targets supported.

For further information, including pricing, please contact us.