Embecosm has extensive experience in all aspects of software modeling of hardware, from the creation of high-level transaction level models (TLM) through to fully cycle accurate simulations.

For firmware development using models of hardware, Embecosm has defined a new standard interface and reference implementation for TLM and cycle accurate modeling using JTAG.

  • Transaction level and cycle accurate modeling.
  • Working from HDL source code when the specification for older IP is missing.
  • Hybrid mixed abstraction level modeling for highly effective SoC model creation.
  • Integration with firmware development and debugging.

Technical Details

Embecosm has the expertise to write new high level transactional models quickly and accurately and is able to wrap existing models with SystemC TLM 2.0. We have particular experience in cycle accurate modeling using the open source Verilator tool, and can provide GNU Debugger implementations which will drive a range of models and silicon seamlessly.

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