Embecosm provides comprehensive services for developing software models of silicon IP, from individual components through to complete Systems-on-Chip. Embecosm’s founder, Dr Jeremy Bennett, is one of the foremost experts on embedded systems modeling and integration with firmware design processes.
SystemC Transaction Level Modeling
Embecosm’s application note on modeling and model reuse was the first publication to explain how to use the new OSCI SystemC TLM 2.0 standard for complete SoCs.
Embecosm has the expertise to write new high level transactional models quickly and accurately and is able to wrap existing models with SystemC TLM 2.0.
SystemC Cycle Accurate Modeling
Embecosm has particular experience in cycle accurate modeling using the Verilator tool (see application notes EAN6 and EAN7). This generates high performance cycle accurate SystemC models from source Verilog, which typically outperform the best proprietary event-driven simulators.
Verilator models follow strict zero-delay synthesis semantics, using 2-value logic. As such they are far closer to gate level simulation and the behavior of the final chip. This means they find bugs due to dependencies on ‘X’ and ‘Z’ behavior which conventional simulators miss.
Hybrid modeling mixes models of different levels of abstraction. For example, fast high level models of processor cores are often available, yet hand writing high-level models of all the associated peripheral logic on a SoC would be far too time consuming.
Alternatively peripheral logic can be modeled directly from the Verilog HDL using Verilator. Although these cycle accurate models are slower most peripherals are used relatively infrequently so there is little effect on overall model performance. The complete SoC model is available much earlier, and hand-writing effort can be concentrated on key peripheral logic which is heavily used.
This approach can be highly effective. In one example an 80MHz 3-4 million gate SoC with two ARM cores could be modelled in real-time by combining high speed core models with cycle accurate models of the peripherals.
The Embecosm approach ensures that the firmware development team have a consistent and reliable debugging interface from initial system design all the way through to functional silicon.
Integration with Firmware Development and Debug
Embecosm specialises in the integration of hardware models with firmware development and debugging, and has created the Unified SoC Development Environment to enable this. We can provide GNU Debugger implementations that will drive a range of models and silicon seamlessly, either standalone or from within the Eclipse IDE.
The key features of this unique technology are:
- The same debugging interface is presented throughout the design life cycle, from initial model to final silicon.
- The engineer has visibility not just of the processor being debugged, but all the peripherals of the System-on-Chip.
- The implementation uses existing standard protocols and interfaces.
The Embecosm approach ensures that the firmware development team have a consistent and reliable debugging interface from initial system design all the way through to functional silicon. Firmware development can start earlier and is far more productive. By starting early, any problems uncovered in the hardware can be fixed before tapeout, helping to avoid costly silicon re-spins.