High Performance Modeling of Hardware

Embecosm provides a comprehensive service for developing software models of silicon IP, from individual components through to complete Systems-on-Chip. Embecosm's founder, Dr Jeremy Bennett, is one of the foremost experts on modeling embedded systems and their integration within firmware design proceses.

SystemC Transaction Level Modelng

Embecosm's application note on modeling and model reuse was the first publication to explain how to use the new OSCI SystemC TLM 2.0 standard for complete SoCs.

Embecosm has the expertise to write high level transactional models quickly and accurately. More valuable is our expertise in wrapping existing models with SystemC TLM 2.0, thus allowing them to be reused in a wide range of standard environments.

SystemC Cycle Accurate Modelng

Embecosm has particular experience in cycle accurate modeling using the Verilator (see application notes EAN6 and EAN7. This open source tool generates high performance cycle accurate SystemC models from source Verilog, which typically outperform the best proprietary event-driven simulators.

Verilator models follow strict zero-delay synthesis semantics, using 2-value logic. As such they are far closer to gate level simulation and the behavior of the final chip. This means they find bugs due to dependencies on 'X' and 'Z' behavior which conventional simulators miss.

Hybrid Modelng

Hybrid modeling mixes models of different level of abstraction. For example fast high level models of processor cores are often available, yet hand-writing high-level models of all the associated periperhal logic on a SoC would be far to laborious.

Instead the peripheral logic can be modeled directly from the Verilog HDL using Verilator. Although these models, being cycle accurate, are slower, most peripherals are used relatively infrequently, so there is little effect on overall model performance. The complete SoC model is available much earlier, and hand-writing effort can be concentrated on key peripheral logic which is heavily used.

This approach can be highly effective. In one example an 80MHz 3-4 million gate SoC with twin ARM cores could be modelled in real-time by combining high speed models of the cores with cycle accurate models of the peripherals.

Integration with Firmware Development and Debug

Integration of hardware models within the firmware development and debug environment is a speciality of Embecosm, using our Unified SoC Development Environment. We can provide GNU Debugger implementations, which will drive a range of models and silicon seamlessly, either standalone, or within Eclipse. More information....

Availability and Support

Embecosm engineers are available to create models for you and help you with using Verilator.

All services come with an initial 3 month support package, which can be extended as desired.

Embecosm Services

Embecosm provides the following services for customers wishing to adopt this technology.

• Verilator Introductory Package. Intended for users who wish to evaluate Verilator modeling in processor design. Suitable for Verilog IP of up to 50k gates.

  Embecosm engineers spend a minimum of two weeks on the customer's site, installing Verilator and converting the IP to SystemC, while educating the engineering team in use of the tool. This is integrated with a software testbench via JTAG using the Embecosm Unified Debug Interface.

  This service is supplied as a fixed price package.

• Verilator Mainstream Package. For users with complex SoCs who wish to use Verilator models in testing and firmware development.

  Embecosm engineers spend a minimum of four weeks on the customer site. The customer's Verilog is converted to SystemC using Verilator and optimized, while educating the engineering team in use of the tool. Non-synthesizable cells are converted to synthesizable versions for use with Verilator. The complete model is integrated with a software testbench via JTAG using the Embecosm Unified Debug Interface.

  Option. Embecosm can manage introduction of the new GDB port into the mainstream FSF GDB distribution and provide ongoing maintenance of the code to ensure consistency within the mainstream distribution.

  This service can be supplied as a fixed price package.

• SystemC TLM 2.0 Model Wrapping. For customers with existing high performance models which are not TLM 2.0 compliant.

  Embecosm engineers implement high performance SystemC TLM 2.0 wrappers for the existing models, together with a software harness that allows the wrapper to be tested. The resulting models can then we used in a wide range of standard tools and environments.

• SystemC TLM 2.0 Model Creatio. For customers who require specific IP modeled as a SystemC TLM.

  Working from the specification of the IP, Embecosm engineers implement a model of the IP. A separate test bench is created to test the IP and ensure its compliance with the specification.

  Option. With some old IP, the specification may no longer exist. In these cases, Embecosm engineers can work from the Verilog or VHDL source code as specification.

• Hybrid Model Creation. For customers requiring a high performance SoC model in a short timescale.

  Embecosm engineers create cycle accurate models of peripheral logic using Verilator and integrate them with existing high performance processor models. This creates a high performance model of the complete SoC. The Embecosm Unified Debug Interface is used to provide a testbench interface that can be driven from software.

For further information, including pricing, please contact us.