A Student Implementation of AAP for FPGA

I’m yet another work experience student and yet another Daniel. In the summer of 2014 I was tasked with creating a student’s introduction to Verilog. This summer I worked with the skills previously learnt and was tasked with creating a simple processor with Verilog, with the specification of AAP.

Peter Bennett (my partner in crime for this project) and I had almost no clue how to go about making a processor. If you imagine people making processors, you picture some super-intelligent university graduates in rooms with chalkboards floor to ceiling, and we were merely two teenagers finishing GCSEs in a room with just the one whiteboard — which we made the most of, producing our schematic.

We learnt about the different architectures of processors and AAP follows the Harvard architecture, as the memories are separate. This is normally seen as a dastardly thing as it makes lives harder. However, it seemed very logical and approachable for someone who has never played around with processors before.

We were mentored in part by James Pallister. So during the summer we took a trip up to Bristol to visit him at the University of Bristol’s Department of Computer Science, located at the Merchant Venturers building. He helped us a lot during this short expedition from the South Coast, to fix our code and to clarify design points.

Peter and I had nearly finished implementing the instruction set when Peter went off sailing, so I finished the rest of the processor on my own for the final few weeks of summer. The completed application note is now available:

I’ve taken lots away from this experience: I learnt to manage my time, improved my Verilog skills, improved my whiteboard drawing dexterity and enjoyed visiting CERN to assist in a talk on AAP.

I am now undertaking AS-Levels at sixth form. Also I am now working towards my silver duke of Edinburgh award, as part of this I will be volunteering locally by hosting Shrimping workshops.