GSoC Projects: Accelerating RISC-V for AI/ML Applications

Embecosm has been working with Southampton University as an industrial partner for it’s MEng final year Group Design Projects.

The scope of this project was to create a RISC-V based instruction set extension to accelerate AI and machine learning applications. The project used the OpenHW Group’s CV32E40P core as the starting point. In 12 weeks the students were able to produce an instruction set extension that provided a 5.4x execution speed increase versus the unmodified core.

This work has attracted considerable interest. The presentation of the project at the British Computing Societies Open Source Specialist Group has proved very popular on YouTube. The subject is timely: Mitacs recently announced $22.5m of funding in this field.

This project is a starting point. Although the project was aimed at FPGA targets, the timescale of the project meant the design was completed in simulation using Verilator and used proprietary EDA tools. The work continues during 2021 through the Google Summer of Code (GSoC) and the Free and Open Source Silicon Foundation (FOSSi).

We have proposed two projects for GSoC:

  1. Take the existing project in Verilator and bring it up on a standard teaching FPGA board, such as the Nexys A7)[link to project on FOSSI page].
  2. Apply the same approach to a RISC-V core such as PicoRV or SERV, which is small enough to be synthesized using the YoSys tool flow and bring it up on a FPGA board supported by YoSys.

The deadline for applications is 18:00 UTC on April 13 2021. Details of how to apply for GSoC are in the Student Guide. We look forward to your submissions.