A TLM 2.0 socket is the natural model for the bus interface to the
CPU. However the interface to the terminal is much simpler.
Standard byte wide SystemC buffers
(sc_buffer
) will be suitable, one for the Rx
direction and one for Tx. The buffer is implemented for the Rx
direction and a port to a buffer for the Tx direction. The terminal
(see Chapter 7) will offer the complementary
arrangement.
Note | |
---|---|
A SystemC buffer ( |
The interrupt is not modeled as an interface at this stage, so the UART will only be suitable for polled use. An interrupt interface is added in Chapter 10.