Services and Modeling for Embedded Software Development
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5.1. TableGen Requirements

The instruction decoder uses a decode function built by TableGen in order to match instructions to their operands. In order for this function to be built correctly, it is important that only one instruction is mapped to any given bit pattern. If this is not the case then LLVM will fail to compile.

If two instructions do collide, a message such as the following will appear in the build log, identifying which instructions conflicted.

Decoding Conflict: 
        010001.......................... 
        ................................ 
    JR  010001__________________________ 
    RET 010001__________________________ 
        

Conflicts can be solved by providing context as to when it is suitable to decode instructions as one type or another. One way of doing this (if suitable) is to disable an instruction for this stage by either marking it is pseudo (via isPsuedo = 1) or as for use in code generation only (isCodeGen = 1).

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