This SystemC module class is automatically generated by Verilator. The class name is taken from the top level module (orpsoc_fpga_top preceded by V.

The input and output ports of this module are mapped to SystemC sc_in and sc_out ports. Single bit ports are of type bool. Larger ports are of type uint32_t.

In this example there are no ports larger then 32 bits. If there were, then they would use either uint64_t or the SystemC sc_bv types.

	Note
	SystemC offers its own set of types for ports of arbitrary width. However in the reference library, the implementation of these types can be very inefficient. Hence the preference for stdint.h types from C++.

	Caution
	Verilator also supports inout ports, which are mapped to sc_inout. However inout ports are usually associated with tristate logic, for which Verilator currently only has rudimentary support. Thus there are no such ports in this example.