5.1.3. ResetSC

5.1.3. `ResetSC`

This module is used to generate a reset signal at start up for a defined number of clock cycles.

It takes as input port the system clock and for convenience generates both active high and active low reset signals. Only the active low reset signal is used in this application note.

sc_core::sc_in<bool>   clk;
sc_core::sc_out<bool>  rst;
sc_core::sc_out<bool>  rstn;

Constructor

The constructor takes an optional argument of the number of cycles of reset to provide at start up. If not given, this defaults to 5. This is used to initialize the reset counter.

A SystemC method, driveReset is declared which is sensitive to the negative edge of the clock. Releasing the reset on the negative edge of the clock in a cycle-accurate environment means the model will see the released reset first on a positive clock edge.

`driveReset`

This function counts down the reset counter. While the value is positive, it drives the reset signals. Thereafter it releases the signals.

5.1.2. Or1200MonitorSC 5.1.4. TraceSC and OrpsocAccess