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6.2.2.  Direct Access to Verilator Model Signals

The wb_freeze signal is used as an example of direct access. It is declared in rtl/verilog/or1200/or1200_ctrl.v, where it is an input to the module.

input  wb_freeze;

To declare the signal public, a verilator public comment must be inserted before the closing semi-colon.

input  wb_freeze /* verilator public */;

The comment must be before the closing semi-colon.

Verilator will generate all the intervening classes for the signal's full hierarchy (see Section 6.2.1):


The signal can then be accessed from C++, having included the headers for all the intermediate classes:

#include "Vorpsoc_fpga_top_orpsoc_fpga_top.h"
#include "Vorpsoc_fpga_top_or1200_top.h"
#include "Vorpsoc_fpga_top_or1200_cpu.h"
#include "Vorpsoc_fpga_top_or1200_ctrl.h"


  Vorpsoc_fpga_top *orpsoc = new Vorpsoc_fpga_top ("orpsoc");


  bool  wb_freeze = orpsoc->v->or1200_top->or1200_cpu->or1200_ctrl->wb_freeze;

Pitfalls with Direct Access to Signals

Verilator models assume all bits that are not significant to a signal's representation are zero. So if a signal is updated, it is essential that unused bits are masked out.

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