5.2.3. Cache Initialization

The OpenRISC 1000 has optional instruction and data caches. If these are declared (in the or1ksim-board.h header), then they must be enabled by setting the appropriate bit in the supervision register.

This is an example of machine specific initialization.

        /* Cache initialisation. Enable IC and/or DC */
.if IC_ENABLE || DC_ENABLE
        l.mfspr r10,r0,SPR_SR
.if IC_ENABLE
        l.ori   r10,r10,SPR_SR_ICE
.endif
.if DC_ENABLE
        l.ori   r10,r10,SPR_SR_DCE
.endif
        l.mtspr r0,r10,SPR_SR
        l.nop                           /* Flush the pipeline. */
        l.nop
        l.nop
        l.nop
        l.nop
.endif

5.2.2. The _start Function and Stack Initialization 5.2.4. Clearing BSS