The structure of the main program (simpleSocMainSC.cpp) is similar to that for the logger test program (see Section 5.4). The TLM 2.0 header and the headers for each module (Or1ksim ISS, UART and terminal) are included.

#include "tlm.h"
#include "Or1ksimExtSC.h"
#include "UartSC.h"
#include "TermSC.h"
	  

As before the main program (sc_main) takes as arguments the Or1ksim configuration file and OpenRISC 1000 image. Instances of the three modules are declared.

  Or1ksimExtSC  iss( "or1ksim", argv[1], argv[2] );
  UartSC        uart( "uart", iss.isLittleEndian() );
  TermSC        term( "terminal" );
	  

The endianness for the UART is set using the public utility function in Or1ksimExtSC. The TLM sockets of UART and ISS can be connected:

  iss.dataBus( uart.bus );
	  

The Rx buffer in the UART is connected to the Tx port in the terminal and the Rx buffer in the terminal is connected to the Tx port in the UART.

  uart.tx( term.rx );
  term.tx( uart.rx );
	  

The simulation can then be started with a call to sc_start.