 | Services - tools - models - for embedded software development |
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| Services - tools - models - for embedded software development |
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The GDB architectural specification (gdbarch) for OpenRISC 1000 is fully documented in Embecosm Application Note 3 ([2]). This section notes some important features, which will be of relevance to the RSP server implementation.
All data sizes are specified to match the ABI for the OpenRISC 1000
All memory breakpoints are implemented at the program counter
using the l.trap 1 opcode, which like all
OpenRISC 1000 instructions is 4 bytes long.
This means that after a trap due to a breakpoint, the program
counter must be stepped back, to allow re-execution on resumption
of the instruction that was replaced by l.trap
A total of 35 registers are defined to GDB: The 32 general purpose registers, the previous program counter, the next program counter (colloquially known as the program counter) and the supervision register. There are no pseudo-registers.
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| 4.1.5. Or1ksim: the OpenRISC 1000 Architectural Simulator |  | 4.3. Overview of the RSP Server Implementation |