The complete program is compiled from the top level make
file. Both a standalone program (simple-soc
)
and a libtool compliant library
(libsimple-soc.la
) are created, and both
incorporate the library created when building the logger test (see
Section 5.6). The library provides a
convenient mechanism for reusing the code from this model, when
creating subsequent models which use derived classes.
The Or1ksim configuration is also unchanged. Like the logger, the UART registers start at address 0x90000000 and are a total of 8 bytes in length.
Running the model requires specifying the configuration file
(unchanged) and the binary executable (this time the UART loop
back program). Assuming the programs have been built in a directory
named build
, the following command line is
suitable.
./build/sysc-models/simple-soc simple.cfg progs_or32/uart-loop
The xterm terminal should appear. Select it and type some characters. The window running the model, will show the logged output from the terminal, reporting the same characters being written, as shown in Figure 7.4.
$ ./build/sysc-models/simple-soc simple.cfg progs_or32/uart-loop SystemC 2.2.0 --- May 16 2008 10:30:46 Copyright (c) 1996-2006 by all Contributors ALL RIGHTS RESERVED ... <Or1ksim initialization messages> Read: 'F' Read: 'a' Read: 'r' ... <more Or1ksim output> Read: '!' Read: '!' Read: '!'
Figure 7.4. UART loop back program log output.
At the same time the characters will be echoed on the xterm, as shown in Figure 7.5.
Well it makes a change from "Hello World!".
As an exercise, rebuild the model, removing the call to
wait
in the
Or1ksimExtSC::doTrans
function. Observe that
the program hangs without accepting any characters. The reason for
this is given in the description of doTrans
in Section 6.3.
A debugger connected to the model will show that execution is stuck in Or1ksim ISS, waiting for the data ready flag to be set in the UART. This can never occur, since neither UART nor terminal are given the chance to execute the threads that would set this flag.