The overall class diagram for the decoupled SoC design incorporating a UART and terminal is shown in Figure 9.2. The design is similar to that for the synchronized SoC (see Section 8.2.1). The Or1ksim ISS wrapper and UART are both subclassed to add the behavior needed for decoupled timing. There is no need to subclass the terminal module, since it has no TLM interface, and so therefore cannot use decoupling.
The new Or1ksimDecoupSC
class is associated
with both the system global quantum keeper (tgq
)
and the quantum keeper for the ISS thread
(issQk
).