Events indirect through instructions in the first 256 (0x100) words of instruction memory. In general these should be 32-bit branch instructions, which means event handlers should reside in first or last 2²¹ words of instruction memory.

At present the following event vector locations (word addresses) are defined

The event handling mechanism is still in development. In particular no location is yet defined for the return address to be used by the RTE instruction (see Section 3.7.1).