	Services and Modeling for Embedded Software Development

AAP: An Altruistic Processor

A reference Harvard architecture for embedded compiler development

Simon Cook

Jeremy Bennett

Application Note 13. Issue 2.0

October 2015

Copyright © 2015 Embecosm Limited

Creative Commons License

The document entitled "AAP: An Altruistic Processor" by of Embecosm is licensed under a Creative Commons Attribution 2.0 UK: England & Wales License. See the Legal Notice for details.

Table of Contents

1. Introduction

1.1. Revision History

2. Architecture Description

2.1. Basic architectural features
2.2. Event Handling
2.3. NOP Behavior

3. Instructions

3.1. Notation

3.1.1. Assembler Notation

3.2. Instruction Format

3.3. Summary of Instructions

3.3.1. 16-bit Instructions of AAP
3.3.2. 32-bit Instructions of AAP

3.4. Detailed Descriptions of 16-bit ALU Instructions

3.4.1. NOP: No Operation
3.4.2. ADD: Unsigned Add
3.4.3. SUB: Unsigned Subtract
3.4.4. AND: Bitwise AND
3.4.5. OR: Bitwise OR
3.4.6. XOR: Bitwise Exclusive OR
3.4.7. ASR: Arithmetic Shift Right
3.4.8. LSL: Logical Shift Left
3.4.9. LSR: Logical Shift Right
3.4.10. MOV: Move Register to Register
3.4.11. ADDI: Unsigned Add Immediate
3.4.12. SUBI: Unsigned Subtract Immediate
3.4.13. ASRI: Arithmetic Shift Right Immediate
3.4.14. LSLI: Logical Shift Left Immediate
3.4.15. LSRI: Logical Shift Right Immediate
3.4.16. MOVI: Move Immediate to Register

3.5. Detailed Descriptions of 16-bit Load/Store Instructions

3.5.1. LDB: Indexed Load Byte
3.5.2. LDW: Indexed Load Word
3.5.3. LDB: Indexed Load Byte with Postincrement
3.5.4. LDW: Indexed Load Word with Postincrement
3.5.5. LDB: Indexed Load Byte with Predecrement
3.5.6. LDW: Indexed Load Word with Predecrement
3.5.7. STB: Indexed Store Byte
3.5.8. STW: Indexed Store Word
3.5.9. STB: Indexed Store Byte with Postincrement
3.5.10. STW: Indexed Store Word with Postincrement
3.5.11. STB: Indexed Store Byte with Predecrement
3.5.12. STW: Indexed Store Word with Predecrement

3.6. Detailed Descriptions of 16-bit Branch/Jump Instructions

3.6.1. BRA: Relative Branch
3.6.2. BAL: Relative Branch and Link
3.6.3. BEQ: Relative Branch if Equal
3.6.4. BNE: Relative Branch if Not Equal
3.6.5. BLTS: Relative Branch if Signed Less Than
3.6.6. BGTS: Relative Branch if Signed Greater Than
3.6.7. BLTU: Relative Branch if Unsigned Less Than
3.6.8. BGTU: Relative Branch if Unsigned Greater Than
3.6.9. JMP: Absolute Jump
3.6.10. JAL: Absolute Jump and Link
3.6.11. JEQ: Absolute Jump if Equal
3.6.12. JNE: Absolute Jump if Not Equal
3.6.13. JLTS: Absolute Jump if Signed Less Than
3.6.14. JGTS: Absolute Jump if Signed Greater Than
3.6.15. JLTU: Absolute Jump if Unsigned Less Than
3.6.16. JGTU: Absolute Jump if Unsigned Greater Than

3.7. Detailed Descriptions of 16-bit Miscellaneous Instructions

3.7.1. RTE: Return from Exception

3.8. Detailed Descriptions of 32-bit ALU Instructions

3.8.1. NOP: No Operation
3.8.2. ADD: Unsigned Add
3.8.3. SUB: Unsigned Subtract
3.8.4. AND: Bitwise AND
3.8.5. OR: Bitwise OR
3.8.6. XOR: Bitwise Exclusive OR
3.8.7. ASR: Arithmetic Shift Right
3.8.8. LSL: Logical Shift Left
3.8.9. LSR: Logical Shift Right
3.8.10. MOV: Move Register to Register
3.8.11. ADDI: Unsigned Add Immediate
3.8.12. SUBI: Unsigned Subtract Immediate
3.8.13. ASRI: Arithmetic Shift Right Immediate
3.8.14. LSLI: Logical Shift Left Immediate
3.8.15. LSRI: Logical Shift Right Immediate
3.8.16. MOVI: Move Immediate to Register
3.8.17. ADDC: Unsigned Add with Carry
3.8.18. SUBC: Unsigned Subtract with Carry
3.8.19. ANDI: Bitwise AND Immediate
3.8.20. ORI: Bitwise OR immediate
3.8.21. XORI: Bitwise Exclusive OR Immediate

3.9. Detailed Descriptions of 32-bit Load/Store Instructions

3.9.1. LDB: Indexed Load Byte
3.9.2. LDW: Indexed Load Word
3.9.3. LDB: Indexed Load Byte with Postincrement
3.9.4. LDW: Indexed Load Word with Postincrement
3.9.5. LDB: Indexed Load Byte with Predecrement
3.9.6. LDW: Indexed Load Word with Predecrement
3.9.7. STB: Indexed Store Byte
3.9.8. STW: Indexed Store Word
3.9.9. STB: Indexed Store Byte with Postincrement
3.9.10. STW: Indexed Store Word with Postincrement
3.9.11. STB: Indexed Store Byte with Predecrement
3.9.12. STW: Indexed Store Word with Predecrement

3.10. Detailed Descriptions of 32-bit Branch/Jump Instructions

3.10.1. BRA: Relative Branch
3.10.2. BAL: Relative Branch and Link
3.10.3. BEQ: Relative Branch if Equal
3.10.4. BNE: Relative Branch if Not Equal
3.10.5. BLTS: Relative Branch if Signed Less Than
3.10.6. BGTS: Relative Branch if Signed Greater Than
3.10.7. BLTU: Relative Branch if Unsigned Less Than
3.10.8. BGTU: Relative Branch if Unsigned Greater Than
3.10.9. JMP: Absolute Jump
3.10.10. JAL: Absolute Jump and Link
3.10.11. JEQ: Absolute Jump if Equal
3.10.12. JNE: Absolute Jump if Not Equal
3.10.13. JLTS: Absolute Jump if Signed Less Than
3.10.14. JGTS: Absolute Jump if Signed Greater Than
3.10.15. JLTU: Absolute Jump if Unsigned Less Than
3.10.16. JGTU: Absolute Jump if Unsigned Greater Than
3.10.17. JMPL: Absolute Jump Long
3.10.18. JALL: Absolute Jump Long and Link
3.10.19. JEQL: Absolute Jump Long if Equal
3.10.20. JNEL: Absolute Jump Long if Not Equal
3.10.21. JLTSL: Absolute Jump Long if Signed Less Than
3.10.22. JGTSL: Absolute Jump Long if Signed Greater Than
3.10.23. JLTUL: Absolute Jump Long if Unsigned Less Than
3.10.24. JGTUL: Absolute Jump Long if Unsigned Greater Than

3.11. Detailed Descriptions of 32-bit Miscellaneous Instructions

4.1. Defined Registers
4.2. Calling Convention

Next

Chapter 1. Introduction

Copyright © 2015 Embecosm Limited