3.4.7. ASR: Arithmetic Shift Right

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3.4.7. ASR: Arithmetic Shift Right

Encoding (format 1):

0 0 0 0 1 1 0 d₂ d₁ d₀ a₂ a₁ a₀ b₂ b₁ b₀

Syntax:

ASR R_d,R_a,R_b

Constraints:

a ≤ 7
b ≤ 7
d ≤ 7

Outcome:

R_d ← ( R_a | ( carry << 16 ) ) >> R_b )
carry ← 0
PC ← PC + 1

Notes:

If R_b ≥ 17 the result in R_d will be zero.
The carry flag is always cleared, even if a shift of zero is specified.

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