The command file for this baseline simulation is found in sim/cf-baseline.scr.

The first part of this file sets up the header directories. The local custom directories are specified in preference where appropriate.

+incdir+$BENCH_LOCAL
+incdir+$BENCH_DIR
+incdir+$RTL_LOCAL
+incdir+$RTL_LOCAL/or1200
+incdir+$RTL_DIR/or1200
+incdir+$RTL_DIR/dbg_interface
+incdir+$RTL_DIR/audio
+incdir+$RTL_DIR/ethernet
+incdir+$RTL_DIR/ps2
+incdir+$RTL_DIR/uart16550
+incdir+$RTL_DIR/ssvga
      

As noted earlier, there are multiple instances of timescale.v, with different values for time unit and precision. However with all Verilog files will find the first once, which is in $BENCH_DIR (1ns/10ps).

There are three test bench files: the main ORPSoC test bench and the ORPSoC monitor for l.nop opcodes.

$BENCH_LOCAL/orpsoc_bench.v
$BENCH_LOCAL/or1200_monitor.v
      

The top level module of the DUT, orpsoc_fpga_top is then specified. The bus interconnect instantiated by orpsoc_fpga_top, tc_top, is also specified.

$RTL_LOCAL/orpsoc_fpga_top.v
$RTL_DIR/tc_top.v
      

The sub-components of the FPGA are then specified: the OR1200 CPU, the debug interface, flash and SRAM and audio, Ethernet, keyboard, UART and video peripherals.