The simulation is run with the command:

make simulate COMMAND_FILE=cf-baseline.scr NUM_RUNS=1000
      

The Makefile compiles the target software using the OpenRISC 1000 tool chain, then compiles the simulation with iverilog and runs it with vvp. The compilation is error free:

cd sim/run && time -p iverilog -c iv-processed.scr 
real 1.75
user 1.48
sys 0.30
      

The output from the execution is:

$readmemh(../src/flash.in): Not enough words in the read file for requested rang
e.
(orpsoc_bench.i_orpsoc_fpga.uart_top) UART INFO: Data bus width is 32. Debug Int
erface present.

(orpsoc_bench.i_orpsoc_fpga.uart_top) UART INFO: Doesn't have baudrate output

Execution starts, 1000 runs through Dhrystone
Begin Time = 5
End Time   = 116421
OR1K at 10 MHz  (+PROC_6)
Microseconds for one run through Dhrystone: 116us / 1000 runs
Dhrystones per Second:                      8589 
117975052.00 ns: l.nop report (deaddead)
117986152.00 ns: l.nop exit (00000000)
real 839.00
user 837.40
sys 0.57
      

The warning from $readmemh can be ignored—the OpenRISC 1000 utilities do not pack the program image up to the full size of the actual memory to save file space. There are then a couple of diagnostic messages from the UART

The remainder of the output is generated by the target OpenRISC 1000 program executing within the model. The output is generated by use of l.nop 4, with a report at the end (deaddead) using l.nop 2 and termination with return code 0 using l.nop 1.