A SystemC clock, clk is declared of type sc_clock, which will form the main system clock.

This followed by declarations of signals to connect all the ports on the main ORPSoC module. These include reset, JTAG and all the external peripherals (audio, Ethernet, keyboard, UART and video).

Variables are declared to reference the accessor class (accessor) and SystemC modules (orpsoc, trace, reset, monitor). New instances of these are then instantiated.

The modules are then connected to the signals. The vast majority of these are to the main Vorpsoc_fpga_top instance. The main clock signal is used for both the main system clock and JTAG clock, thus ensuring they will be synchronous.

There are no explicit peripheral models, or JTAG interface, so peripheral input signals are tied off appropriately.

With the modules connected, the model is set to run for an indefinite period by a call to the SystemC function sc_start. Execution will only terminate if the program being executed includes a l.nop 1 opcode, which will cause the monitor module to call the SystemC function sc_stop.

If and when execution does terminate, the space allocated for modules is deleted before the sc_main function returns.