Services - tools - models - for embedded software development
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Chapter 6.  Building the Initial Verilator Model

6.1. Fixing the Initial Errors
6.2. Accessing Signals in Verilator Models
6.2.1. Module Hierarchy When Accessing Signals
6.2.2. Direct Access to Verilator Model Signals
6.2.3. Access to Verilator Model Signals via Tasks and Functions
6.2.4. Good Coding Practice when Accessing Verilator Signals
6.3. VCD Tracing
6.3.1. Constructor for the VCD Trace Module
6.3.2. Destructor for the VCD Trace Module
6.3.3. The trace method, driveTrace
6.4. Building the Complete Model
6.5. Baseline Verilator Performance
6.5.1. Comparison with Event Driven Simulation

Building a Verilator model has a number of traps for the unwary

So it is not uncommon for Verilator to immediately throw errors on RTL which is supposedly clean and synthesizable.

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