Services and Modeling for Embedded Software Development
Embecosm divider strip
Prev  Next

Chapter 2.  Background to SystemC and the TLM 2.0 Standard

2.1. What is SystemC
2.2. What is a TLM
2.2.1. Hardware and Software Views of Parallelism
2.2.2. Modeling Hardware Parallelism in Software
2.3. Overview of OSCI TLM 2.0
2.3.1. Transaction Payload
2.3.2. Initiators and Targets
2.3.3. Blocking, Non-Blocking, Debug and Direct Memory Interfaces
2.3.4. Loosely Timed, Approximately Timed and Untimed TLM
2.3.5. TLM 2.0 Convenience Sockets

The development of SystemC as a standard for modeling hardware started in 1996. Version 2.0 of the proposed standard was released by the Open SystemC Initiative (OSCI) in 2002. In 2006, SystemC became IEEE standard 1666-2005 [5].

OSCI has several groups working on supplementary standards. One of these is the TLM Working Group. It proposed its first standard for transaction level modeling in 2005. Two drafts for version 2.0 were released in 2006 and 2007. The version 2.0 standard issued in June 2008, with a minor update (2.0.1) issued in June 2009 [6].

Embecosm divider strip