If the DLAB bit is set in the line control register, then reads to the first two registers (read buffer and interrupt enable) yield instead the low and high bytes of the divisor latch.

Reading the read buffer (when DLAB=0) yields the byte just read, if flag DR is set in the line status register. The act of reading causes the DR flag and the read buffer full interrupt to be cleared. If no interrupts remain pending then the interrupt pending flag is cleared.

Reading the interrupt indicator register clears the transmit buffer empty interrupt if it was pending. If no interrupts remain pending, then the interrupt pending flag is cleared.

Reading the line status register clears any error indications and the receive line status interrupt if it was pending, although the model has no way of setting any of these indications. If no interrupts remain pending, then the interrupt pending flag is cleared.

Reading the modem status register clears all flags and the modem status interrupt if it was pending. However the modem loopback indication may still be in operation and if so the bits and interrupts are set to indicate the state of the loopback by a call to modemloopback. If no interrupts remain pending, then the interrupt pending flag is cleared.