If the DLAB bit is set in the line control register, then writes to the first two registers (read buffer and interrupt enable) update the low and high bytes of the divisor latch respectively.

Writing the transmit hold register (when DLAB=0) triggers a new transfer. The flags are set to indicate data is in the register, the transmit buffer empty interrupt is cleared, and the bus thread (busThread) notified via the SystemC event txReceived. If no interrupts remain pending, then the interrupt pending flag is cleared.

If the modem loopback bit is set by a write to the modem control register, then the modem status bits are set appropriately by a call to modemLoopback. If enabled a modem status interrupt may be generated.