A sequence diagram, illustrating the handling of a write transaction for the design is shown in Figure 7.2. For simplification, the setting up of the transport call by the Or1ksim wrapper is not shown, since this is the same as for the logger example (see Figure 5.2). As a further simplification the UART is shown writing to the receive buffer of the terminal directly, whereas in detail this is via the sc_out port of the UART and a connecting sc_signal.

When a sequence of memory mapped reads and write lead to a byte being received in the UART's transmit buffer, the UART target port handler signals the bus handling thread using the txReceived SystemC event. The UART's bus handling thread then passes that byte to the terminal's buffer, where it can be written to the screen.

Figure 7.2.  Sequence diagram for a write transaction with the Or1ksim simple SoC.

Note

The notification of the byte arrival is an asynchronous activity. It triggers behavior in a separate thread of the UART. Although not conventional UML notation, the two threads are shown as separate lines under the UART to make this clear. Similarly the transfer to the terminal's receive buffer is an asynchronous activity, with a new thread of control (a SystemC SC_METHOD). It is the existence of these separate threads of control which requires the Or1ksim wrapper to execute wait, to allow those threads a chance to execute.