The class definition (in UartSyncSC.h) includes the header of the base class and defines two new constants to represent the delay in reading and writing in nanoseconds.

#define UART_READ_NS       60   // Time to access the UART for read
#define UART_WRITE_NS      60   // Time to access the UART for write
	  

The class is derived directly from the base class, UartSC. A new custom constructor is needed, with an additional parameter specifying the input clock rate. This is used in conjunction with the divisor latch to specify the baud rate.

  UartSyncSC( sc_core::sc_module_name  name,
              unsigned long int        _clockRate,
              bool                     _isLittleEndian );
	  

The busThread thread is reimplemented to add the timing delay (as a call to wait in transmitting a character as described above).

The blocking transport function, busReadWrite is reimplemented to add in the bus delays in reading and writing. Again this will be achieved by calls to wait, so keeping the model synchronous.

The busWrite must also be reimplemented, since any change to the divisor latch or the line control register (which specifies the bit format being sent on the wire) could affect the baud rate and timing for busThread

A new utility function, resetCharDelay is defined to compute the delay in putting a character on the Tx port from the clock rate, divisor latch and line control register.

Two new member variables are declared, to hold the clock rate and the calculated delay to put a character on the Tx port.

The implementation of the UART module class with synchronized timing, UartSyncSC may be found in sys-models/sync-soc/UartSyncSC.h in the distribution.