 | Services and Modeling for Embedded Software Development |
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| Services and Modeling for Embedded Software Development |
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A new class, UartSyncSC derived from
UartSC implements the additional functionality
for synchronized timing.
The time taken for the serial pulses (start, data, parity, stop bits) on the real UART will be modeled as a delay before writing data onto the Tx output port. The corresponding delay on the Rx buffer port will be modeled by the terminal writing into that port[8].
The TLM 2.0 socket modeling the bus is extended to model the time taken for reads to and writes from the bus.
[8] This is not the ideal solution. The delay is really a property of the channel, so should be modeled by a derived class of the standard SystemC buffer which provides a defined delay between data being written and data availability being signaled. The approach used here (transmitter models the delay) represents a practical compromise.
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8.3.3.
Or1ksimSyncSC Module Class Implementation
|  | 8.4.1.
UartSyncSC Module Class Definition
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