Chapter 8. Adding Synchronous Timing to the Model

8.1. Summary of Changes Required for Synchronous Timing

8.2. Overall Design of the Synchronized SoC Model

8.2.1. Class Structure
8.2.2. Behavioral Diagrams

8.3. Extending the Or1ksimExtSC Wrapper Module

8.3.1. Adding Clock Rate and Timing Functions to the Or1ksim Library
8.3.2. Or1ksimSyncSC Module Class Definition
8.3.3. Or1ksimSyncSC Module Class Implementation

8.4. Extending the UartSC Module Class

8.4.1. UartSyncSC Module Class Definition
8.4.2. UartSyncSC Module Class Implementation

8.5. Extending the TermSC Module Class

8.5.1. TermSyncSC Module Class Definition
8.5.2. TermSyncSC Module Class Implementation

8.6. Main Program for the Synchronous Model

8.7. Compiling and Running the Synchronous Model

The current models are all untimed. In the TLM 2.0 components (Or1ksimExtSC and UartSC) the delay parameter to the blocking transport function has been ignored by setting it to zero.

In this section, the models are extended to synchronize explicitly with the SystemC clock.

The synchronization is not perfect—the underlying Or1ksim ISS executes outside the SystemC world. Synchronization is only possible when it makes an upcall for read or write. In Chapter 9 this model will be further extended to add control over the underlying ISS and its interaction with SystemC time.

The code for the timed UART module (UartSyncSC.cpp and UartSyncSC.h), The code for the timed terminal module (TermSyncSC.cpp and TermSyncSC.h), the code for the timed Or1ksim ISS wrapper (Or1ksimSyncSC.cpp and Or1ksimSyncSC.h) and the main program for the complete model (syncSocMain.cpp) may be founded in the sysc-models/sync-soc directory of the distribution.