A sequence diagram, illustrating the handling of a transaction for the design is shown in Figure 8.2. Only the handling of the transaction by the wrapper is shown, since there is no significant change in the interactions of the UART and terminal (see Section 7.1.2).

Before each upcall transaction, the Or1ksim wrapper class waits for the period of time used by the underlying Or1ksim ISS. This brings all other threads into synchronization, giving them the opportunity to catch up.

After each upcall transaction is complete, the timing point of the underlying Or1ksim ISS is reset to zero.

Figure 8.2.  Sequence diagram for the Or1ksim SoC with synchronized timing, showing the timing calls.