The overall class diagram for the synchronized SoC design incorporating a UART and terminal is shown in Figure 8.1. The design is almost identical to that for the simple SoC (see Section 7.1.1). The only difference is that the Or1ksim ISS wrapper, UART and terminal modules are all subclassed to add the behavior needed for synchronized timing.

Figure 8.1.  Class diagram for the Or1ksim SoC with synchronized timing.