The overall class diagram for the SoC with interrupts
incorporating a UART and terminal is shown in Figure 10.2. The design is similar
to that for the temporally decoupled SoC (see Section 9.3.1). The
Or1ksim ISS wrapper and UART are both
subclassed to add the behavior needed for interrupt handling. There is
no need to subclass the terminal module, since it has no interrupts
to be modeled.
The new Or1ksimIntrSC class is associated
with an array of 32 signals, which may be connected to peripherals
wishing to raise an interrupt.
The new UartIntrSC class is associated with a
SystemC FIFO used to collect interrupts raised from both Rx and
Tx ports. It also has a SystemC output port,
intr on which it drives any interrupt it raises.
