10.3.2. UartIntrSC Module Class Implementation

10.3.2. `UartIntrSC` Module Class Implementation

Since this class declares a new SystemC process, SC_HAS_PROCESS is used. The constructor passes its arguments to the base class, UartDecoupSC and sets the FIFO queue size to 1.

UartIntrSC::UartIntrSC( sc_core::sc_module_name  name,
                        unsigned long int        _clockRate,
                        bool                     _isLittleEndian ) :
  UartDecoupSC( name, _clockRate, _isLittleEndian ),
  intrQueue( 1 )
{

Note

	Note
The choice of FIFO size means that there should be only one request for interrupt pending. In principle this could block an attempt by the `rxMethod` to write to the FIFO, and since SystemC methods may not wait (unlike threads) a run time error will occur. This is an explicit model design decision. If there is interrupt congestion, then it would be useful to know—indicating design issues over the UART capacity. If this were not an issue, then it would be quite valid to use a larger FIFO capacity.

The choice of FIFO size means that there should be only one request for interrupt pending. In principle this could block an attempt by the rxMethod to write to the FIFO, and since SystemC methods may not wait (unlike threads) a run time error will occur.

This is an explicit model design decision. If there is interrupt congestion, then it would be useful to know—indicating design issues over the UART capacity. If this were not an issue, then it would be quite valid to use a larger FIFO capacity.

The constructor then creates the new SystemC method for intrThread.

intrThread has a very simple API. If true is read it asserts an interrupt (drives the interrupt port true), otherwise it deasserts the interrupt port (drives the interrupt port false).

On initialization, the interrupt port is deasserted (false). The thread then sits in a perpetual loop, copying requests from the FIFO to the interrupt signal output port.

  while( true ) {
    intr.write( intrQueue.read() );
  }

The interrupt generator, genIntr is almost identical to the version in the base class, UartSC. The only difference is that if an interrupt is generated, a request to drive the signal is written onto the internal interrupt FIFO for processing by the intrThread thread.

    setIntrFlags();                    // Show highest priority
    intrQueue.write( true );            // Request an interrupt signal

The interrupt clear routing is a similar modification, this time requesting the interrupt signal to be cleared by writing false on the FIFO queue.

  if( isSet( regs.iir, UART_IIR_IPEND )) {     // 1 = not pending
    intrQueue.write( false );                   // Deassert if none left

The implementation of the UART module class with interrupts, UartIntrSC may be found in sys-models/intr-soc/UartIntrSC.cpp in the distribution.