Rerunning the Verilator build without warnings disabled on the new command file now yields 135 warnings (the previous problem, VARHIDDEN counts as a pair of warnings, one for the variable being hidden and one for the variable doing the hiding):

%Warning-IMPLICIT: ../orp_soc/rtl/verilog/dbg_interface/dbg_top.v:881: Signal de
finition not found, creating implicitly: RegAccess
%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around so
urce to disable this message.
%Warning-IMPLICIT: ../orp_soc/rtl/verilog/dbg_interface/dbg_top.v:886: Signal de
finition not found, creating implicitly: RISCAccess

...
	

Verilog allows signals to be used if they have not been declared. This is generally considered bad practice, and Verilator warns if it is found. There are five such occurrences in ORPSoC two in dbg_top.v, two in uart_regs.v and one in ps2_top. These are corrected by inserting their correct definition.

A performance run with the revised command file cf-optimized-3.scr gives no significant change in performance at 42.50 kHz.