The Open SystemC Initiative (OSCI) has issued the second version of its standard for Transaction Level Modeling (TLM) in June 2008 [6]. This defines an interface for writing high level software models of hardware. An updated version (TLM 2.0.1) was released in July 2009.

The OSCI standard is comprehensive. As well as a powerful general purpose interface, it defines a number of convenience components to facilitate adoption of the technology.

This application note provides an introductory tutorial on using TLM 2.0 for loosely timed models—ideally suited for early development of embedded software. It demonstrates through a practical case study the development of a complete SoC, capable of running a modern Linux 2.6 kernel, using the TLM 2.0 convenience components.

One of the most important components in any SoC system model is the processor core Instruction Set Simulator (ISS). This application note demonstrates how to wrap an existing ISS to provide a TLM 2.0 compliant interface.

This application note is the first in a series from Embecosm (www.embecosm.com), providing case studies in OSCI TLM 2.0 use. The objective is to provide an introduction to TLM 2.0 within a practical context. Examples are provided throughout, based on open source components, which are freely reusable under the GNU General Public License.