Chapter 3. The Example Design

3.1. Memory Map

3.2. Interrupt Assignment

3.3. Test Bench Modeling of Peripherals

3.4. Test Software Application

3.5. Use of the OpenRISC 1000 l.nop Instruction

3.6. Module Hierarchy and File Organization

3.6.1. Distribution Code Organization

3.7. Modifications to the ORPSoC Code

3.8. Building the Example

3.8.1. Command Files
3.8.2. Additional Flags

The demonstration system is based on a fully configured ORPSoC with data and instruction caches, data and instruction MMUs, multiply and divide instructions, 2MB Flash and 2MB SRAM. SRAM and all other memories are implemented as generic flip-flop memory. Flash memory is modeled as generic SRAM initialized from a file.