 | Services - tools - models - for embedded software development |
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| Services - tools - models - for embedded software development |
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The OpenRISC 1000 CPU incorporates a programmable interrupt controller, capable of handling up to 20 interrupt lines. These are assigned as shown in Table 3.1.
|
Number |
Assignment |
|---|---|
|
0-1 |
Unused |
|
2 |
UART |
|
3 |
Unused |
|
4 |
Ethernet |
|
5 |
PS/2 |
|
6-19 |
Unused |
Table 3.1. ORPSoC interrupt assignment
| |  | |
| 3.1. Memory Map |  | 3.3. Test Bench Modeling of Peripherals |