6.1. Details of the 16450 UART

The 16450 UART is a very long established industry component. Data written a byte at a time into the transmit buffer is converted to serial pulses on the output (Tx) pin. Serial pulses on the input (Rx) pin are recognized and converted to byte values, which can be read from the receive buffer. Typically Rx and Tx are connected to a terminal and keyboard which can generate and recognize the pulses of data. The UART can also generate additional signals for terminals and keyboards to provide physical flow control, but that is beyond the scope of this model. The key interfaces are shown in Figure 6.1.

Figure 6.1. 16450 UART: Key interfaces.

The 16450 UART specifies a set of registers which control the UART behavior. On the Tx/Rx side, this includes setting the board rate and the pattern of stop, start and data bits. On the CPU side this includes configuring interrupt behavior (if any) and setting flags to show the status of transmit and receive buffers. The registers are shown in Table 6.1.

Address	Register	R/W	Description
0	`RXBUF`	R	When the `DLAB` bit is 0 (see register `LCR`, this is the buffer for read data.
	`TXBUF`	W	When the `DLAB` bit is 0 (see register `LCR`, this is the buffer for data to be written.
	`DLL`	R/W	When the `DLAB` bit is 1 (see register `LCR`, this is the low byte of the divisor latch (which controls UART performance)
1	`IER`	R/W	The interrupt enable register. The lower 4 bits control which events generate an interrupt.
1	`DLH`	R/W	When the `DLAB` bit is 1 (see register `LCR`, this is the high byte of the divisor latch (which controls UART performance)
2	`IIR`	R	Interrupt identification register. Bit 0 indicates if an interrupt is pending, bits 1-2 the reason for the interrupt.
3	`LCR`	R/W	Line control register. Various bits controlling the behavior of the UART. Of these, `DLAB`, bit 7, the divisor latch access bit is important, because it controls the behavior of registers 0 (`RXBUF`/`TXBUF`/`DLL`) and 1 (`IER`/`DLH`).
4	`MCR`	W	Modem control register. Bits 0-4 control the behavior of the modem.
5	`LSR`	R	Line status register. Bits 0-6 report the status of the UART. Of these, DR, bit 0, receiver data ready is important, indicating there is valid data in `RXBUF`.
6	`MSR`	R	Modem Status Register. Bits reporting the state of the modem.
7	`SCR`	R/W	Scratch register. Not used by the UART, but may be used by the application to store an 8-bit value.

Table 6.1. NS 16450 UART Registers