A transaction level model cannot show all the intricacies of a UART—the whole point is to simplify and remove detail.

The TLM should allow the CPU to read and write registers and communicate with a model terminal/keyboard which will send and receive characters and generate interrupts as appropriate. While all writable registers can be written and all readable registers read, only those registers and bits of registers which are relevant to this level of modeling will have any impact on behavior.